Technical Field
This disclosure is directed to the design of integrated circuits, and in particular, the design of clock distribution networks.
Description of the Related Art
Integrated circuits (ICs) often include at least one clock distribution network, sometimes referred to as a clock tree, for distributing a clock signal to clocked circuits. A generated clock signal may be provided to a root node at a root level of the clock tree and distributed through a number of branches. At the end of each branch is are leaf nodes at a leaf level of the clock tree. From each leaf node, the clock signal is provided to one or more clocked circuits. In between the root level and the leaf level may be one or intermediate levels.
Clock gating circuits may be implemented at each of the various levels of a clock tree. The clock gating circuits may be uses to selectively inhibit or enable the clock signal from passing to the next level of the clock tree, and ultimately to the clocked circuits. Inhibiting the clock signal using clock gating circuits may be performed when certain clocked circuits are idle or otherwise not performing useful work. This may in turn result in power savings.
In additional to having clock gating circuits at various levels of the clock tree, inverters and/or buffers may also be implemented. The implementation of inverters and/or buffers in various branches of the clock tree adjust the timing skew of that particular branch such that the clock signal is provided from each of the leaf nodes at substantially the same time.